RTL Engineers should have proficency in Verilog or VHDL, and experience running through a standard FPGA flow. Knowledge of Chisel and a VLSI synthesis flow is a plus.
Experience with Cadence or Synopsys EDA tools, at minimum being able to go from RTL handoff through place and route.
Experience with bringing up basic toolchain and compiler systems up for a new target architecture. LLVM experience is perferred, but not necessary.